Microcomputer and method for developing system program

ABSTRACT

There are provided a central processing unit ( 2 ), a high-speed serial communication interface circuit which can be utilized for a debugging interface, for example, a USB interface circuit ( 3 ), and an external bus interface circuit ( 5 ) which can be connected to an external memory. The USB interface circuit has a plurality of input buffers (EP  1 , EP  2 ) therein and data can be output from one of the input buffers in parallel with an input operation to the other input buffer. In a debugging mode, the USB interface circuit receives a system program, and the system program thus received can be output from the external bus interface circuit together with a memory access control signal. When a target program is to be downloaded from a host computer into a target system, a speed of a data transfer can be increased.

FIELD OF THE INVENTION

The present invention relates to a microcomputer, and particularly, amicrocomputer having a debugging support function, and furthermore, amethod for developing a system program which operates the microcomputer.

BACKGROUND OF THE INVENTION

A microcomputer having a debugging support function includes a debugginginterface for carrying out a communication with an emulator or a hostcomputer in the debugging. For example, a serial input/output interfacebased on a JTAG (Joint Test Action Group, IEEE std 1149.1, IEEE StandardTest Access Port and Boundary-Scan Architecture) protocol is used forthe debugging interface. Patent Document 1 has also described amicrocomputer having such a debugging interface.

-   Patent Document 1: JP-A-2002-202900 (Paragraph 0017)

SUMMARY OF THE INVENTION

The inventor investigated an increase in a speed of a data transfer in afunction for downloading a target program from a host computer into aprogram memory of a target system when a microcomputer having adebugging support function (which will also be referred to as an on-chipdebugging function) is subjected to system debugging (a debugging targetmicrocomputer will be referred to as a target microcomputer). Forexample, the target microcomputer has a debugging serial interfacecircuit based on the JTAG. An emulator is connected to a personalcomputer (PC) having a USB (Universal Serial Bus) interface circuitthrough a USB cable, and is connected to a debugging serial interface ofthe target microcomputer mounted on a target system (which will also bereferred to as a user system) through a dedicated user interface cable.The target microcomputer has the on-chip debugging function. The targetmicrocomputer having the on-chip debugging function has a debugging modefor supporting a development of the target program in addition to a usermode. In the user mode, a system program (which will also be referred toas a target program) to be a user program developed for the targetsystem by a user is executed. In the debugging mode, when the executionof the user program is stopped, a program for a program debuggingsupport (which will also be referred to as a debugging support program)is mainly executed. The debugging support program is transferred byemulator software over the host computer every time a power supply ofthe target microcomputer is turned on, and is written onto a debuggingaddress space in the target microcomputer and is linked to the emulatorsoftware on the host computer. The target microcomputer executes thedebugging support program in the user mode so that the user programsupplied from the host computer is written to a predetermined memoryspace on the target system. The debugging serial interface circuit basedon the JTAG is used in the communication between the emulator and thetarget microcomputer. The debugging serial interface circuit carries outa serial transfer which is clock synchronous on a unit of apredetermined byte. Therefore, a transfer speed is proportional to theclock frequency and is lower than that in the USB interface circuit. Forexample, a transfer throughput is 1200 kilobytes (KB)/second in a fullspeed in the USB standards 1.1. However, the interface based on the JTAGrequires a data transfer procedure for acquiring a status indicative ofan access permission from the target microcomputer every maximum datatransfer, for example, 4 bytes and setting next transfer data. Becauseof an overhead, a transfer speed limit, for example, 230 KB/second isgenerated even if a synchronous clock frequency is increased. Theinventor found that a long time is required for a load transfer of atarget program having a comparatively large capacity due to a differencein the transfer speed and a system debugging efficiency is reduced,resulting in one of factors for inhibiting a reduction in a developmentperiod for the target program.

It is an object of the invention to increase a speed of a data transferwhen downloading a debugging target system program from a host computerinto a target system in the case in which a target microcomputer issubjected to system debugging.

It is another object of the invention to contribute to a reduction in adevelopment period for a system program in respect of an increase in aspeed of a data transfer when downloading a debugging target systemprogram from a host computer into a target system in the case in whichan emulator is utilized to develop the system program.

The above and other objects and novel features of the invention will beapparent from the description of the specification and the accompanyingdrawings.

The summary of the typical invention disclosed in the application willbe briefly described below.

[1] A microcomputer according to the invention comprises a centralprocessing unit, a high-speed serial communication interface circuit (3)which can be utilized for a debugging interface, and an external businterface circuit (5) which can be connected to an external memory. Thehigh-speed serial communication interface circuit has a plurality ofinput buffers (EP 1, EP 2) therein and data can be mutually output fromone of the input buffers in parallel with an input operation to theother input buffer. The high-speed serial communication interfacecircuit receives a system program in the debugging mode and the systemprogram thus received can be output from the external bus interfacecircuit together with a memory access control signal. The high-speedserial communication interface circuit is a universal serial businterface circuit, for example. In the system debugging, the hostcomputer is directly connected to the high-speed serial communicationinterface circuit. Consequently, it is possible to increase a speed of adata transfer when downloading a target program from the host computerto the target system. In particular, the speed of the data transfer canfurther be increased in that the high-speed serial communicationinterface circuit has the two-plane buffers which can mutually switchinput/output operations to carry out parallel operations. The increasein the speed of the data transfer in the download of the target programfrom the host computer to the target system can contribute to areduction in a period for developing the target program.

In a desirable configuration according to the invention, there isprovided a direct memory access controller capable of carrying out acontrol to transfer the received system program to a memory connected tothe external bus interface circuit. It is convenient for a reduction ina burden on the central processing unit and a further increase in thespeed of the data transfer. A transfer source of the system programthrough the direct memory access controller is an input buffer of thehigh-speed serial communication interface circuit, for example. In thecase in which there is provided a random access memory (7) capable oftemporarily storing a system program received by an input buffer of thehigh-speed serial communication interface circuit, a transfer source ofthe system program through the direct memory access controller may bethe random access memory. The multistage buffer is constituted by theinput buffers (EP 1, EP 2) of the high-speed serial communicationinterface circuit and the random access memory (7) to receive the systemprogram. Therefore, there is further room for a difference in a speedbetween the receipt processing of the high-speed serial communicationinterface circuit and the transfer processing for the received data.

In a desirable configuration according to the invention, there isprovided a debugging dedicated low-speed serial communication interfacecircuit (8), the debugging dedicated low-speed serial communicationinterface circuit being usable for inputting control data to control thehigh-speed serial communication interface circuit in the debugging mode.The debugging dedicated low-speed serial communication interface circuitis a serial interface circuit based on the JTAG, for example, and cancarry out an interface operation without requiring the control of thecentral processing unit. For example, the debugging dedicated low-speedserial communication interface circuit is usable for receiving thesystem program in place of the high-speed serial communication interfacecircuit in the debugging mode.

In respect of the completeness of the debugging support function, atrace control circuit may be included. The trace control circuitsuccessively stores, as trace information, an internal state obtainedwhen the central processing unit executes the system program. The traceinformation thus stored is output to an outside after the execution ofthe system program is stopped. The high-speed serial communicationinterface circuit can be utilized for an external output of the traceinformation.

[2] A method for developing a system program according to the inventionserves to develop a system program which is to be executed by a targetdevice by using a host computer (25), an emulator (35) and a targetdevice (33), and comprises a first processing of storing a systemprogram output through a high-speed serial communication by the hostcomputer in one of two-plane buffers as a processing to be carried outby the emulator, a second processing of transmitting a system programstored in the other buffer to the target device through a low-speedserial communication in parallel with the first processing, and a thirdprocessing of carrying out a handshake control of the low-speed serialcommunication together with the target device. By utilizing thetwo-plane buffers, it is possible to increase the speed of the datatransfer when downloading the target program from the host computer intothe target system. In this respect, it is possible to shorten a periodfor developing the target program.

In a specific configuration according to the invention, the systemprogram output from the buffer is transmitted through the low-speedserial communication to the target device via an FIFO buffer having astorage capacity which is equal to or larger than that of one of thebuffers in the second processing, and a transmission from the FIFObuffer to the target device is carried out in response to a transmissionpermission sent from the target device, thereby suppressing a transferfrom the buffer to the FIFO buffer in response to a full state of theFIFO buffer in the third processing. By using the FIFO buffer in thelow-speed serial communication, it is possible to decrease aninterruption of the first processing due to the stay of the data to betransferred from the first processing to the second processing. Also inthis respect, it is possible to increase the speed of the data transfer.

[3] A microcomputer (1) according to the invention has a user mode and adebugging mode, and comprises a central processing unit (2), a universalserial bus interface circuit (3), an ROM (71) retaining a firstdebugging control program, an RAM (7), and an external bus interfacecircuit (5). The universal serial bus interface circuit has apredetermined endpoint buffer circuit (20) which can be utilized in thedebugging mode, the predetermined endpoint buffer circuit has a pair ofbuffers (EP 1, EP 2) which can be operated in parallel, and one of thebuffers can be caused to carry out an input operation and the otherbuffer can be caused to carry out an output operation in paralleltherewith. The microcomputer to be a target is a target microcomputer,and is supposed to be directly connected to the host computer for adebugging support through the universal serial bus interface circuit.

When the debugging mode is designated in a power-on reset, the centralprocessing unit executes the first debugging control program toinitialize the universal serial bus interface circuit to be operable, asecond debugging control program is received by the universal serial businterface circuit, the second debugging control program thus received isstored in the RAM, and a transition to an execution of the seconddebugging control program stored in the RAM is made. Consequently, it ispossible to download the second debugging control program to betransferred through the emulator software over the host computer at ahigh speed every time the power supply of the microcomputer is turnedon, for example. Consequently, it is possible to increase a speed of arise in a debugging controllable state which is linked to the emulatorsoftware over the host computer.

As a specific configuration according to the invention, there is furtherprovided a buffer RAM and a direct memory access controller, and thecentral processing unit causes the direct memory access controller totransfer the user program received by the universal serial bus interfacecircuit to the buffer RAM in response to a download request commandreceived by the universal serial bus interface circuit in accordancewith the second debugging control program. In the debugging controllablestate, it is possible to increase the speed of the download of the userprogram. As a desirable configuration according to the invention,furthermore, the central processing unit causes the direct memory accesscontroller to carry out a control to transfer a program transmitted tothe buffer RAM through an external bus interface circuit to the externalprogram memory in response to a transfer request command received by theuniversal serial bus interface circuit in accordance with the seconddebugging control program. Then, the central processing unit makes atransition to the user mode in response to a mode control command in anexecution state of the second debugging control program, and the centralprocessing unit fetches an instruction from the program memory throughthe external bus interface circuit in the user mode, thereby executingthe user program. By tracing and analyzing the execution state of theuser program, the user program is debugged.

[4] A microcomputer (40) according to the invention in another respectcomprises a central processing unit (44), a universal serial businterface circuit (48), an ROM (45) retaining a first debugging controlprogram, a buffer RAM (47), and an external interface circuit (41), andthe universal serial bus interface circuit has a predetermined endpointbuffer circuit (20), the predetermined endpoint buffer circuit has apair of buffers (EP 1, EP 2) which can be operated in parallel, and oneof the buffers can be caused to carry out an input operation and theother buffer can be caused to carry out an output operation in paralleltherewith. In a power-on reset, the central processing unit executes thefirst debugging control program to initialize the universal serial businterface circuit to be operable, a second debugging control program isreceived by the universal serial bus interface circuit, the seconddebugging control program thus received is stored in the buffer RAM, andthe second debugging control program stored in the buffer RAM is outputthrough the external interface circuit. The microcomputer to be thetarget is a microcomputer for a control of the emulator (33) to bedisposed between the target microcomputer and the host computer for adebugging support.

As a specific configuration according to the invention, themicrocomputer further comprises a direct memory access controller (46),and the direct memory access controller transfers the second debuggingcontrol program from the buffer RAM to an outside through the externalinterface circuit in accordance with a transfer control condition set bythe central processing unit.

Brief description will be given to advantages obtained by the typicalinvention disclosed in the application.

More specifically, it is possible to increase the speed of the datatransfer when downloading the system program from the host computer intothe target system in the case in which the target microcomputer issubjected to the system debugging. In short, it is possible to enhancethe performance of the system program downloading function in the systemdebugging.

In the case in which the emulator is utilized to develop the systemprogram, the period for developing the system program can be shortenedin respect of an increase in the speed of the data transfer whendownloading the system program from the host computer into the targetsystem.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a microcomputer according to theinvention,

FIG. 2 is an explanatory view showing a connecting configuration of atarget system mounting a microcomputer including a USBIF and a hostcomputer,

FIG. 3 is an explanatory view showing a connecting configuration of atarget system mounting a microcomputer having no USBIF and the hostcomputer,

FIG. 4 is a block diagram showing an example of the microcomputer inFIG. 3 and an emulator,

FIG. 5 is a logical circuit diagram showing the details of a JTAGinterface logic constituted by an FPGA,

FIG. 6 is a timing chart showing an operation to be carried out by thestructure of FIG. 5,

FIG. 7 is a flowchart showing a control procedure for switchingtwo-plane buffers BUF 1 and BUF 2 of an RAM to transfer data to anFIFOTDO,

FIG. 8 is a timing chart showing a difference in an operation timing ofa program download in each of cases in FIGS. 5 and 9,

FIG. 9 is a block diagram illustrating an emulator according to acomparative example of FIG. 5,

FIG. 10 is an explanatory chart illustrating a download performanceobtained when downloading a user program file from the host computer ineach of the example of FIG. 5 and the comparative example of FIG. 9,

FIG. 11 is a block diagram showing a more specific example of themicrocomputer according to the invention,

FIG. 12 is a timing chart illustrating an operation timing of on-chipdebugging which is obtained by the microcomputer,

FIG. 13 is an explanatory diagram showing a communication format of aUSB,

FIG. 14 is a flowchart illustrating a basic form of a communicationhandshake control of the host computer and a USB interface circuit,

FIG. 15 is a flowchart illustrating handshake control contents betweenthe host computer and the USB interface circuit in the case in whichforcible break is carried out during the execution of a user program,

FIG. 16 is a flowchart illustrating control contents of the download ofsoftware from the host computer into the USB interface circuit,

FIG. 17 is a block diagram showing a variant of the microcomputer inFIG. 1, and

FIG. 18 is a block diagram showing a variant of the microcomputer inFIG. 17.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates a microcomputer 1 according to the invention. Themicrocomputer 1 is formed on a semiconductor substrate (semiconductorchip) such as single crystal silicon by a complementary MOS integratedcircuit manufacturing technique. The microcomputer 1 comprises a centralprocessing unit (CPU) 2, a USB interface circuit (USBIF) 3 to be ahigh-speed serial communication interface circuit which can be utilizedfor a debugging interface, an external bus interface circuit (EXIF) 5which can be connected to an external memory (EXMRY) 4, a direct memoryaccess controller (DMAC) 6, a random access memory (RAM) 7, a JTAGinterface circuit (JTAGIF) 8 to be a debugging dedicated low-speedserial communication interface, a trace control circuit (TRCNT) 9, anAUD (advanced user debugging) interface circuit (AUDIF) 10 forcontrolling an external output of trace information, and an emulationRAM (EMMRY) 11, and they share an internal bus (IBUS) 12, which is notparticularly restricted. Another circuit such as a timer counter may beconnected to the internal bus 12. The RAM 7 is utilized as a buffer RAMor the like for temporarily holding transfer data.

The USBIF 3 is based on USB2.0 standards, for example, and has a USBbuffer portion (BEP) 20 and a USB interface control portion (UCNT) 21.The USB buffer portion 20 has a double buffer structure by USB buffersEP 1 and EP 2 having 512 bytes respectively. The USB buffers EP 1 and EP2 are constituted by an FIFO, for example. The UCNT 21 carries out aso-called USB device control and data transfer control. The UCNT 21 isconnected as a USB host to a USB host mounted on the host computer(personal computer) in FIG. 1 through a USB cable 23, and a serialtransmitting/receiving control of data is performed as the USB devicecontrol in a predetermined protocol in response to a command sent fromthe USB host. Data received from the USB host are transmitted to thebuffer portion 20 and data to be transmitted to the USB host aresupplied from the buffer portion 20. The UCNT 21 carries out aread/write control for the buffer portion 20 and a control for atransfer request for the DMAC 6 as the data transfer control. In theread/write control for the buffer portion 20, particularly, it ispossible to mutually carry out a data output operation from one of theUSB buffers (an output operation to the internal bus 12 for a DMAtransfer) in parallel with an input operation to the other USB buffer (areceived data input operation from the USB host).

A data transfer control condition such as a transfer source address or atransfer destination address is set by the CPU 2 so that the DMAC 6controls a data transfer from a transfer source to a transfer operationin response to a DMA transfer request given from the USBIF 3 or thelike. Both a dual addressing mode and a single addressing mode aresupported as a data transfer mode. For example, it is possible tocontrol a data transfer to be carried out by a single address betweenthe USB buffers EP 1 and EP 2 and the EMMRY 11, a data transfer to becarried out by a single address between the USB buffers EP 1 and EP 2and the RAM 7, and a data transfer to be carried out by a dual addressbetween the RAM 7 and the EXMRY 4.

The JTAGIF 8 has an input register TDI for inputting received data, anoutput register TDO for outputting data to be transmitted, a dataregister SDDR for connecting the register TDI to the internal bus 12, acommand register which is not shown, and a JTAG control circuit (JCNT)24. The JCNT 24 controls a serial output from the register TDO and aserial input to the register TDI synchronously with a clock signal TCK.A so-called TAP (test-access-port) control is used for the control, andthe control is carried out depending on a pattern of a 1-bit mode selectsignal (not shown) which is serially input synchronously with the clocksignal TCK. A data input from an outside to the JTAGIF 8 can be carriedout every time an access permission bit is output from the register TDOto the outside. For example, the JTAGIF 8 outputs the access permissionbit to the outside for a 4-byte receipt. In this meaning, a serialcommunication speed obtained by the JTAGIF 8 is low. In the standards, aTCK frequency is several tens MHz and is lower than a transferthroughput of 480 MB/second at a high speed in the USB2.0 standards.

The CPU 2 includes an instruction control portion and a calculatingportion which are not shown. The instruction control portion controls aninstruction fetch and decodes the fetched instruction. The calculatingportion carries out a data calculation and an address calculation byusing an instruction decode signal and an operand specified by aninstruction, thereby executing the instruction. The microcomputer 1 hasa debugging mode for supporting a development of a target program inaddition to a user mode to be a normal mode. The debugging mode can bespecified through a mode terminal in a reset or a break interruption inthe user mode. In the user mode, a system program stored in the EXMRY 4(which will also be referred to as a user program) is executed. In thedebugging mode, when the execution of the user program is stopped, aprogram for supporting program debugging (a debugging support program)is mainly executed. The debugging support program is transferred by theemulator software of a host computer 25 every time the power supply ofthe microcomputer 1 is turned on, and is written onto an address spacefor debugging of the EMMRY 11. A boot program is retained by a mask ROM(not shown) provided in the microcomputer 1 or an electricallyrewritable flash memory. In the debugging, the microcomputer 1 executesthe debugging support program in the debugging mode so that the userprogram is written to the EXMRY 4 over the target system. The userprogram is supplied from the host computer 25.

In FIG. 1, the USBIF 3 can be utilized for a communication between themicrocomputer 1 of the target system and the host computer 25. TheJTAGIF 8 can also be utilized and the USBIF 3 is more excellent inrespect of a communication speed. Therefore, the utilization of theUSBIF 3 is the best way. In particular, the USBIF 3 includes thetwo-plane buffers EP 1 and EP 2 which can alternately switchinput/output operations to carry out a parallel operation. In thisrespect, it is possible to implement a further increase in the speed ofthe data transfer. In respect of an increase in the speed of the datatransfer in the download of the user program from the host computer 25into the target system, it is possible to shorten a period for thedevelopment of the user program.

In order to transfer the system program received by the USBIF 3 to theEXMRY 4 connected to the EXIF 5, it is preferable to use the DMAC 6. Thetransfer source of the system program through the DMAC 6 is the inputbuffers EP 1 and EP 2 of the USBIF 3, for example. In the case in whichthe system program received by the input buffers EP 1 and EP 2 of theUSBIF 3 is temporarily stored in the RAM 7, it is preferable that thesystem program should be first transferred from the buffers EP 1 and EP2 to the RAM 7 through the DMAC 6 and should be transferred from the RAM7 to the EXMRY 4 in a proper timing. A multistage buffer is constitutedby the input buffers EP 1 and EP 2 of the USBIF 3 and the RAM 7 toreceive the system program. Consequently, it is possible to have afurther margin for a difference in a speed between the receiptprocessing of the USBIF 3 and a transfer processing to an outside forthe received data.

The JTAGIF 8 can be utilized for the input of control data forcontrolling the USBIF 3 in the debugging mode. The JTAGIF 8 can beutilized for the receipt of the system program in place of the USBIF 3in the debugging mode, for example. There is the necessity in anenvironment in which the use of the USBIF 3 is reserved in the user modeand the USBIF 3 cannot be utilized for the program download in the usermode. The USBIF 3 may have such a structure as to include a plurality oftransfer channels. If one of them is dedicated to on-chip debugging, itis not necessary to carry out the program download in an alternatecommunication through the JTAGIF 8. Therefore, an increase in the speedof the data transfer can be guaranteed.

The TRCNT 9 is a circuit for sequentially storing an internal state ofthe CPU 2 through a trace bus 13 when the CPU 2 executes the userprogram. A place for storage is set to be an FIFO buffer (FBUF) 26 andan address control for the FIFO buffer 26 is carried out by an addresscounter (ACOUNT) 27. Trace information stored in the FIFO buffer 26 canbe transferred to the host computer 25 by means of the USBIF 3 or theJTAGIF 8 in the debugging mode. Since the FIFO buffer 26 has a smallcapacity, it is unsuitable for tracing a large amount of data. In thecase in which the large amount of data are collected as the traceinformation, the AUDIF 10 is used. It is preferable that addressinformation and data information of the internal bus 12 should be storedin a trace buffer (TRBUF) 28 every bus access cycle and data in theTRBUF 28 should be output to an outside synchronously with a clocksignal AUDCLK. AUDATA indicates output data and AUDSYNC indicates a dataoutput synchronization signal.

Alternatively, the trace information stored in the FIFO buffer 26 can betemporarily stored in the RAM 7 and the EXMRY 4 and can also be outputin a batch by using the USBIF 3.

FIG. 2 shows a connecting configuration of a target system 30 mountingthe microcomputer 1 and the host computer 25. The target system 30 isprovided with a USB connector 31 to be connected to the USBIF 3 of themicrocomputer 1, and it is preferable that the USB connector 31 and aUSB connector of the host computer 25 should be directly connected toeach other through the USB cable 23. The microcomputer 1 has a debuggingfunction. Therefore, it is possible to download a system program to be atarget program and a debugging support program without providing anemulator between the host computer 25 and the microcomputer 1. In asubsequent user mode, the trace information is collected during theexecution of the system program. When the execution of the systemprogram is broken to make a transition to the debugging mode, anevaluation for the target system and a correction of the system programare carried out with reference to the trace information.

FIG. 3 shows a connecting configuration of a target system 34 mounting amicrocomputer 33 which does not include the USBIF 3 and the hostcomputer 25 as another example. An emulator 35 is disposed between thetarget system 34 and the host computer 25. The emulator 35 and the hostcomputer 25 are connected to each other through the USB cable 23. Thetarget system 34 and the emulator 35 are connected to each other througha JTAG interface cable 36.

FIG. 4 shows an example of the microcomputer 33 and the emulator 35. Themicrocomputer 33 is different from the microcomputer 1 in FIG. 1 in thatthe USBIF 3 is not provided. Circuit elements having the same functionsare indicated by the same reference numerals and detailed descriptionthereof will be omitted.

The emulator 35 is constituted by a microcomputer 40, a fieldprogrammable gate array (FPGA) 41, and a synchronous static randomaccess memory (SSRAM) 42.

The microcomputer 40 has a CPU 44, an ROM 45, a DMAC 46, an RAM 47 and aUSBIF 48 and is formed on a semiconductor substrate. The USBIF 48 isconstituted by a USB buffer portion 20 having USB buffers EP 1 and EP 2on two planes and a UCNT 21, and is based on the USB2.0 standards in thesame manner as the USBIF 3. The RAM 47 constitutes a 2-plane RAM bufferin a second stage for information stored in the USB buffers EP 1 and EP2, and a first RAM buffer region BUF 1 and a second RAM buffer regionBUF 2 are assigned. It is desirable to provide dual ports havingindividual access ports for the first RAM buffer region BUF 1 and thesecond RAM buffer region BUF 2. More specifically, when the USB bufferEP 1 stores data received from a host computer 25, data to be outputfrom the USB buffer EP 2 can be stored in the first RAM buffer regionBUF 1 of the RAM 47 and data stored in the second buffer region BUF 2can be output from a predetermined port to an outside at the same time.When the USB buffer EP 2 stores the data received from the host computer25, moreover, the data output from the USB buffer EP 1 can be stored inthe second RAM buffer region BUF 2 of the RAM 47 and data stored in thefirst RAM buffer region BUF 1 can be output from a predetermined port tothe outside at the same time. It is desirable to use the DMAC 46 for adata transfer from the USBIF 48 to the RAM 47.

The FPGA 41 is a circuit which has a large number of nonvolatile storageunits such as a flash memory cell and can desirably set a logicalfunction corresponding to a programming state of the nonvolatile storageunits. The FPGA 41 constitutes a JTAG interface logic 41A fortransmitting/receiving data to/from a JTAGIF 8 of the microcomputer 33,and an address generating logic 41B for carrying out an access controlof the SSRAM 42.

The JTAG interface logic 41A has an output FIFO buffer FIFOTDO, an inputbuffer TDI, and an interface control circuit (JCNT) 50. In a data writeto the output FIFO buffer FIFOTDO from the RAM 47, the CPU 44 forexecuting a USB interface control program manages a writable state(TDOST) to the output FIFO buffer FIFOTDO, an empty state (TDOF) and thelike, and continuously sets transfer data to the output FIFO bufferFIFOTDO. The JCNT 50 monitors an access permission bit sent from theJTAGIF 8 of the microcomputer 33. When the access permission bit isenabled, 4-byte information is transmitted from the output FIFO bufferFIFOTDO. The information transmitted from the output FIFO buffer FIFOTDOis received by the JTAGIF 8 of the microcomputer 33 and is stored in adata register SDDR. When the information is stored in the data registerSDDR, a DMAC 6 is started and the information is written to an EXMRY 14through a DMA transfer.

The SSRAM 42 is utilized for storing trace information output from anAUDIF 10 of the microcomputer 33. An address generating logic forcarrying out the access control of the SSRAM 42 implemented by the FPGA41 constitutes an address counter (ACOUNT) 52 and a selector (ASEL) 53.The selector 53 selects whether the addressing of the SSRAM 42 iscarried out by the CPU 44 or the address counter 52. The selection isdetermined in accordance with an instruction of the CPU 44.

Thus, the 2-plane buffers constituted by the buffers BUF 1 and BUF 2capable of inputting and outputting received data in parallel, and theoutput FIFO buffer FIFOTDO capable of storing the received data outputfrom one of the two-plane buffers in an FIFO format are provided betweenthe USBIF 48 connected to the host computer 25 and the JTAGIF 8 of thetarget computer 33. Therefore, the host computer 25 and themicrocomputer 33 are not directly connected to each other through theUISB interface. However, it is possible to increase a data transferefficiency to some extent.

In particular, the built-in RAM 47 is set to have a double bufferstructure having several kilobytes and the processing is carried out inparallel in such a manner that the data held in one of the buffers BFU 1and BFU 2 are written to the output FIFO buffer FIFOTDO during thereceipt of the data downloaded from the host computer 25 to the otherbuffer BFU 1 or BFU 2. Also in the case in which data sizes of thebuffers EP 1 and EP 2 are different from the data size of the bufferFIFOTDO and it is necessary to put a restriction that the DMAC transferis not interrupted in the middle because the operations of the buffersEP 1 and EP 2 and the operation of the buffer FIFOTDO are independent ofeach other, therefore, it is possible to take a countermeasure.

FIG. 5 shows the details of the JTAG interface logic 41A constituted bythe FPGA 41. FIG. 6 shows an operation timing in FIG. 5.

The buffer FIFOTDO has a multistage structure of 4 bytes by 61 stages(244 bytes). 55 denotes an interface to be connected to themicrocomputer 40. The buffer FIFOTDO is constituted by an FIFO 56 and ashift register 57. A control block 58 and a buffer control block 59constitute the JCNT 50. 59A and 59B indicate a predetermined logic.CPUDATA (REGDATA.D) indicates data output from the RAM 47, CPUWR_N(TDOWR_N) indicates a write request for the FIFO 56, TDOREG.Q indicatesread data transmitted from the FIFO 56, RDREQ indicates a read requestfor the FIFO 56, and SHIFTREG.Q indicates output data (TDO output) ofthe shift register 57. SBUF_LOAD indicates a data load signal of theshift register 57 and S_P indicates a shift signal of the shift register57. TDOem indicates an empty signal of the FIFO 56 and TDOfl indicates afull signal of the FIFO 56. TDOST indicates whether a write to thebuffer FIFOTDO can be carried out or not, and 1 indicates “writable” and0 indicates “non-writable”. In the TDOF, 1 indicates that all the dataof the buffer FIFOTDO are shifted out and 0 indicates that any of thedata of the buffer FIFOTDO are not shifted out (an initial value).TDOINT indicates a signal for outputting an interruption request signalIRQ when all of the data of the buffer FIFOTDO are shifted out, and 1indicates that an interruption request can be given and 0 indicates thesuppression of the interruption request (an initial value).

The data (REGDATA.D) are written to the FIFO 56 in a CPU clock CPUCLKsynchronization in response to the write enable (TDOWR_N) through theRAM 47 of the microcomputer 40. When the FIFO 56 is set in a full state,the TDOfl is output synchronously with the CPU clock CPUCLK. When theFIFO 56 is set in an empty state, the TDOem is output synchronously witha clock TCK. A data transfer start load pulse (SBUF_LOAD) to be sent tothe shift register 57 is generated synchronously with the write enable(TDOWR_N) when the FIFO 56 is empty, and is generated synchronously witha transfer end pulse (DONE_P) when the FIFO 56 is not empty. Thisfunction is implemented by the logics 59A and 59B. The DONE_P isgenerated based on the access permission bit sent from the targetmicrocomputer 33. The access permission bit is input through theregister TDI. In the buffer control block 59, the TDOfl indicative of adata writable state of the FIFO 56 is checked every data transfer end ofthe shift register 57. The TDOfl generates a TDOST bit indicative of awritable state of the buffer FIFOTDO and the TDOF bit indicative of theempty state of the buffer FIFOTDO is generated by the TDOem and theDONE_P, thereby reflecting the JTAG register of the control block 58. Inthe case in which the TDOF is used for an interruption request to begiven to the microcomputer 40, an interruption request signal IRQ isgenerated by the TDOINT bit indicative of an interruption permission andthe TDOF. When the CPU 44 accepts the interruption request, switching toa next RAM buffer (S7) in the execution of a TDO data set processing inFIG. 7 is carried out.

FIG. 7 shows a control procedure for switching the two-plane RAM buffersBUF 1 and BUF 2 of the RAM 47 and transferring data to the bufferFIFOTDO. First of all, the TDOINT capable of carrying out the controlprocedure is set to be 1 (S1) and whether the buffer FIFOTDO is empty ischecked depending on whether the TDOST is equal to 1 or not (S2). If thebuffer FIFOTDO has a vacancy, data are transferred to the buffer FIFOTDO(S3). A byte number of the transferred data is checked. Morespecifically, it is decided whether the number is a maximum capacitynumber in a region to be assigned to each of the buffers BUF 1 and BUF 2(S4). When the transfer byte number is reached, the vacancy of theFIFOTDO is checked depending on a decision whether the TDOF is equal to1 or not (S5). If it is decided that a shift-out is completely carriedout, an interruption request is given to the CPU 44 through the IRQ, andthe TDOF is cleared to be 0 (S6). Then, a transfer source RAM bufferregion is switched into the next buffer BUF 1 or BUF2 (S7). Theprocessing is repeated till the completion of the transmission (S8).After the completion, the TDINT is cleared to be 0 (S9) and the controlis ended.

In the data write transfer from the buffer BUF 1 to the buffer FIFOTDO,thus, a kilobyte number of a maximum capacity of the RAM 47 istransferred with reference to the writable state (TDOST bit) of thebuffer FIFOTDO and the empty state (TDOF) of the buffer FIFOTDO is thenconfirmed, and subsequently, switching to the next buffer BUF 2 or BUF 1is carried out and this processing is repeated until a specified datavolume is transferred completely. In a data write from the RAM 47 to thebuffer FIFOTDO, consequently, the TDOST bit and the TDOF bit are managedto continuously set the transfer data. The access permission bittransmitted from the microcomputer 33 to the buffer TDI is monitored bythe hard logic 58. As a result, an overhead is eliminated from thedetection of the access permission bit to the transfer of the data and acontinuous transfer of several hundreds bytes at a maximum can becarried out so that a speed of a download transfer of a user program canbe increased as shown in FIG. 8(A). Also in the case in which the targetmicrocomputer does not have the USBIF 3, the program download transferspeed can be increased to some extent. In FIG. 8(A), a microcomputerwrite implies a data transfer write from the RAM 47 to the bufferFIFOTDO. The JTAG output implies a transfer data output from the bufferFIFOTDO to the target microcomputer 33. SP represents a status pollingprocessing of the access permission bit from the target microcomputer33.

FIG. 9 illustrates an emulator according to a comparative example. A USBis used for an interface with a host computer. A USB driver 61 and a USBcontroller microcomputer chip 62 are provided. A program of the USBcontroller microcomputer chip 62 is stored in an ROM 63 and an SDRAM 64is utilized as a work memory. The received USB data are once stored inthe SDRAM 64 and data are stored in the SDRAM 64 through a USB packetanalysis and the like and are then transmitted from a data outputregister of a JTAG controller 65 to a target microcomputer. In aninterface based on the JTAG, the end of the transmitted data is carriedout in a status acquiring mode in which an access permission bit can bereceived from a target CPU in a software download data transfer method.Moreover, a data transfer amount for each time is 4 bytes at a maximum.The emulator acquires an access permission bit indicative of the end ofthe status acquiring mode from the target microcomputer 33 everytransfer. In short, the access permission bit is to be acquired duringpolling to set transfer data to the data output register (TDO). In thiscase, as shown in FIG. 8(B), an overhead T1 is generated from thedetection of the access permission bit to the set of the transfer data.In brief, the data are set to the data output register (TDO) every4-byte transfer in FIG. 8(B) and the data are previously set to the dataoutput register (TDO) and are output in a 4-byte unit for each accesspermission bit acquirement by the hard logic 58 in FIG. 8(A).

FIG. 10 shows a download performance in the case in which a user programfile of 1 megabyte is downloaded from a host computer PC into anexternal memory of the target microcomputer in relation to the exampleof FIG. 5 and the comparative example of FIG. 9. A trend line “a”corresponds to FIG. 5 and a trend line “b” corresponds to FIG. 9. Whendata are to be transferred from the host computer to the targetmicrocomputer, consequently, the program download performance in thecomparative example of FIG. 9 is not changed but maintained to be 230KB/second at TCK=10 MHz or more.

In the example of FIG. 5, the download performance is enhanced linearlyat TCK=10 MHz or more. In case of TCK=20 MHz, moreover, the downloadperformance is 400 KB/second which is approximately a double.

FIG. 11 shows a further specific example of the microcomputer 1. FIG. 11is different from FIG. 1 in that a plurality of USB buffer portions (BEP0 to BEP 6) 20 is provided in a USB interface circuit 3. Furthermore,there is shown an ROM 71 retaining a boot program. An emulation memory11 is constituted by an SRAM and the ROM 71 is constituted by anelectrically rewritable nonvolatile memory such as a mask ROM, an EEPROMor a flash memory. In addition, a break circuit 72 is provided. In thebreak circuit 72, a break condition is set through a CPU 2 in adebugging mode and the generation of a coincident state with the breakcondition is detected in a user mode, and a request for a breakexception is given to the CPU 2.

Each of the BEP 0 to BEP 6 of the USB buffer portions 20 implies an FIFO(First-In First-Out) buffer which is referred to as an endpoint in theUSB standards. The FIFO buffer has such a double buffer structure as toprepare for an input (IN) and an output (OUT) respectively, and isconstituted like the EP 1 and EP 2 shown in FIG. 1. It is to beunderstood that the BEP 0 is an endpoint 0 and the BEP 6 is an endpoint6. A number of the endpoint is an example. A maximum number of theendpoint which can be possessed by a USB device is defined based on theUSB standards. The endpoint 0 (BEP 0) is used for a control transfer andis indispensable to the USB device. The USB interface circuit 3 can beutilized in both a user mode and a debugging mode. In the USB bufferportions (BEP 0 to BEP 6) 20, the BEP1 and the BEP2 are dedicated to ause based on a user program and the BEP 3 to the BEP6 are dedicated to adebugging support. The BEP 0 is shared by both of them. The BEP 0 isused for a control transfer of descriptor information dedicated toon-chip debugging. The BEP 3 is utilized for a bulk-out transfer of USBdata. The BEP 4 is utilized for a bulk-in transfer of the USB data. TheBEP 5 is utilized for inputting an instruction command. The BEP 6 isutilized for outputting status information. The BEP 1 and the BEP 2 areutilized for inputting/outputting data in accordance with the set of auser in the user mode. The USB interface circuit 3 is operatedsynchronously with a clock signal CLK having a frequency of 48 MHz, forexample, which is given from an outside. The CLK may be generatedthrough a PLL circuit in a microcomputer 1.

A boot program retained in the ROM 71 is not particularly restricted butis set to be a USB initialization control program for initializing theUSB interface circuit 3 and a transfer control program. The transfercontrol program serves to store, in the emulation memory 11, a debuggingsupport program (which will also be referred to as ASE firm software)received through the USB interface circuit 3.

A system controller (an SYSC 74) is connected as an external terminalshown typically to a debugging mode terminal ASEMD and a reset terminalRES, and furthermore, a power-on reset signal output from a power-onreset circuit (PORES) 73 is supplied to control an operation mode of themicrocomputer 1 in accordance with their inputs. In the SYSC 74, a usermode is designated by the debugging mode terminal ASEMD. When a power-onreset instruction is given from the power-on reset circuit 73 or a resetinstruction is given from the reset terminal RES, a CPU 2 is initializedin response to a control signal φ1. The CPU 2 executes the USBinitialization control program retained in the ROM 71 to enable theoperations of the endpoints BEP 0, BEP 1 and BEP 2 to be carried out. Inthe CPU 2, finally, the execution of an instruction given from a headaddress in a program storage region can be started. On the other hand,in the SYSC 74, a debugging mode is designated by the debugging modeterminal ASEMD. When a power-on reset instruction is given from thepower-on reset circuit 73, the CPU 2 is initialized in response to acontrol signal φ2 so that the CPU 2 executes the USB initializationcontrol program retained in the ROM 71 to enable the endpoints BEP 0 toBEP 6 to be operated. Then, the CPU 2 executes the transfer controlprogram retained in the ROM 71 to store, in the emulation memory 11, adebugging support program (which will also be referred to as ASE firmsoftware) received through the USB interface circuit 3. Finally, the CPU2 is caused to enable the transferred ASE firm software to be executed.In a state in which the user program branched into the user mode isexecuted in the debugging mode, a reset instruction in the debuggingmode itself is masked even if the reset instruction of the RES is given.The reason is that a jump to a reset vector through a reset input isenabled to be verified when the user program branched from the debuggingmode to the user mode is executed.

In the case in which a user program is downloaded from a host computer25 by the ASE firm software, the CPU 2 causes a DMAC 6 to transfer theuser program received by the USBIF 3 to a buffer RAM 7 in response to adownload request command received by the USBIF 3 in accordance with theASE firm software. For example, after a communication with the USBIF 3is completed, the CPU 2 causes the DMAC 6 to carry out a control totransfer a program transmitted to the buffer RAM 7 to an external memory4 through an external bus interface circuit 5 in response to a transferrequest command received by the USBIF 3 in accordance with the ASE firmsoftware. The CPU 2 can make a transition to the user mode in responseto a mode control command in the execution state of the ASE firmsoftware. In the user mode, the CPU 2 can fetch and execute aninstruction sent from the external memory 4.

FIG. 12 illustrates an operation timing of on-chip debugging to becarried out by the microcomputer. At a time of t0, the ASEMD is set tohave a low level and an instruction for a debugging mode is given. Whena power supply is turned on at a time of t1 and an instruction for apower-on reset is given from the power-on reset circuit 73 (a time oft2), the control signal φ2 is activated so that the CPU 2 isinitialized. The CPU 2 executes the USB initialization control programretained in the ROM 71 to carry out a USB boot processing, therebyenabling the operations of the endpoints BEP 0 to BEP 6 to be carriedout. Then, the CPU 2 executes the transfer control program retained inthe ROM 71. More specifically, when a write command is received by theUSB interface circuit 3, a debugging support program (which will also bereferred to as ASE firm software) received through the USB interfacecircuit 3 is stored in the emulation memory 11 in response to the writecommand (an ASE firm write processing). After the ASE firm writeprocessing is ended, the USB interface circuit 3 receives a breakcommand from the host computer so that the CPU 2 can execute the ASEfirm software over the EMMRY 11. When the USB interface circuit 3receives a user program execution command from the host computer, then,a processing is branched into an address of the user program designatedthrough the user program execution command so that the CPU 2 is causedto make a transition to the user mode for executing the user program. Inthe execution state of the user program, when the USB interface circuit3 receives a break command, for example, a break exception request BERQis issued to the CPU 2 so that the execution of the user program carriedout by the CPU 2 is stopped and the CPU 2 is thus caused to make atransition to the debugging mode for executing the ASE firm softwareagain.

FIG. 13 illustrates a communication format of the USB. A head of oneframe is set to be SOF (Start of frame). DATA0/DATA1 is set to be a datapacket for on-chip debugging in the frame of the USB communicationformat in the USB standards. Read/write of the DATA0/DATA1 is carriedout by each BEP. The USB packet data for the on-chip debugging areconstituted by a header and data. The header includes information aboutan identification ID, a data size, a status and an instruction command.The data information include information about download data.

FIG. 14 illustrates a basic form of a communication handshake control ofthe host computer 25 (PC side) and the USB interface circuit 3. A USBdata packet transmitted from the host computer 25 is received by an EP3. Next, the CPU 2 reads and analyzes the USB data packet received bythe EP 3 in accordance with the ASE firm program, and carries out acontrol corresponding to a result of the analysis and transmits a resultof the control from an EP 4 to the host computer 25.

FIG. 15 illustrates the contents of the handshake control between thehost computer 25 and the USB interface control 3 in the case in which aforcible break is carried out during the execution of a user program. AnEP 5 is used as an instruction command receipt dedicated buffer. Aninstruction command packet received by the EP 5 is analyzed and arequest for a break exception processing is given from a USB controlcircuit 21 to the CPU 2 in response thereto, and a vector address of theASE firm is given. The CPU 2 jumps from the execution state of the userprogram to an address of the break of the ASE firm program. The USBinterface control circuit 21 receives a break acknowledge BACK from theCPU 2, and sets status information (BACK) to an EP 6 and transmits thestatus information to the host computer 25. The host computer 25ascertains whether the status is set in a breaking state or not.

FIG. 16 illustrates the contents of the control of a download ofsoftware (a user program) from the host computer 25 to the USB interfacecircuit 3. A transfer size and a load destination address aretransmitted to the BEP 3 together with a software download transmissionrequest by the host computer 25. On the other hand, a transmissionpermission is transferred from the CPU 2 to the host computer 25 throughthe BEP 4. When the transfer is completed, download data are transmittedfrom the host computer 25 to the USB interface circuit 3 correspondingto a designated size. At this time, if the same data are received to theBEP 3 of the USB interface circuit 3, a DMA transfer is carried out todirectly write the same data to an external memory 4 by a USBinterruption. When the transmission is completed corresponding to adesignated size, the completion of the transmission is transferred tothe host computer 25 through the EP 4.

FIG. 17 shows a further example of the microcomputer 1. FIG. 17 isdifferent from FIG. 11 in that the JTAGIF 8 and the AUDIF 10 aredeleted, and furthermore, the USBIF 3 is dedicated to a debugging mode.The USBIF 3 does not include the BEP 1 and the BEP2. The USBIF 3 cannotbe utilized as a user resource. The USBIF 3 can be used in only on-chipdebugging. The AUDIF 10 is not required in the case in which an on-chipRAM 7 and an EXMRY 4 to be user resources can be used for storing tracedata having a large capacity.

FIG. 18 shows a further example of the microcomputer 1. FIG. 18 isdifferent from FIG. 17 in that a USBIF 3A is provided as a userdedicated resource. The USBIF 3A includes, as the user dedicatedresources, a buffer 20 having BEP 0, BEP 1 and BEP 2 and a USB interfacecontrol circuit 21A. In each of on-chip debugging and a user mode, aperfectly dedicated USBIF can be utilized.

It is also possible to remove only the AUDIF 10 in FIG. 11, which is notparticularly shown. The USBIF 3 is used in both the on-chip debuggingand the user mode. In the case in which the USBIF 3 is subjected todebugging as the user resource, therefore, it is preferable to utilizethe JTAGIF 8 as a debugging interface.

While the invention made by the inventor has been specifically describedabove based on the embodiment, it is apparent that the invention is notrestricted thereto but various changes can be made without departingfrom the scope thereof.

For example, a cache memory may be disposed between the CPU 2 and theinternal bus 12. In the case in which a virtual address is supported, anaddress converting buffer may be disposed between the CPU 2 and theinternal bus 12. The logics 41A and 41B are not restricted to beconstituted by the FPGA.

The USBIF 3 described with reference to FIG. 11 can be applied to theUSBIF 48 retained in the microcomputer 40 described with reference toFIG. 4. In this case, a user dedicated BEP is not required.

The invention can widely be applied to a microcomputer, andparticularly, a microcomputer having a debugging support function, andfurthermore, a method for developing a system program which operates themicrocomputer.

1. A microcomputer comprising: a central processing unit; a universalserial bus interface circuit which can be utilized as a debugginginterface; and an external bus interface circuit which can be connectedto an external memory, wherein the universal serial bus interfacecircuit includes a plurality of input buffers, and data is output fromone of said input buffers in parallel with an input operation to anotherof said input buffers, wherein the universal serial bus interfacecircuit receives a system program in a debugging mode, and the systemprogram thus received can be output from the external bus interfacecircuit together with a memory access control signal, wherein themicrocomputer further comprises a direct memory access controllerconfigured to perform a control to transfer the received system programto a memory connected to the external bus interface, and wherein atransfer source of the system program through the direct memory accesscontroller is one of said input buffers of the universal serial businterface circuit.
 2. A microcomputer comprising: a central processingunit; a universal serial bus interface circuit which can be utilized asa debugging interface; and an external bus interface circuit which canbe connected to an external memory, wherein the universal serial businterface circuit includes a plurality of input buffers, and data isoutput from one of said input buffers in parallel with an inputoperation to another of said input buffers, wherein the universal serialbus interface circuit receives a system program in a debugging mode, andthe system program thus received can be output from the external businterface circuit together with a memory access control signal, whereinthe microcomputer further comprises: a direct memory access controllerconfigured to perform a control to transfer the received system programto the external memory connected to the external bus interface; and arandom access memory configured to temporarily store the system programreceived by said one input buffer of the universal serial bus interfacecircuit, wherein a transfer source of the system program through thedirect memory access controller is the random access memory.
 3. Amicrocomputer comprising: a central processing unit; a high-speed serialcommunication interface circuit which can be utilized as a debugginginterface; and an external bus interface circuit which can be connectedto an external memory, wherein the high-speed serial communicationinterface circuit includes a plurality of input buffers therein, anddata is output from one of said input buffers in parallel with an inputoperation to another of said input buffers, and the high-speed serialcommunication interface circuit is configured to receive a systemprogram in the debugging mode, and the system program thus received canbe output from the external bus interface circuit together with a memoryaccess control signal, wherein the microcomputer further comprises adebugging dedicated low-speed serial communication interface circuitwhich is usable to input control data to control the high-speed serialcommunication interface circuit in the debugging mode, and the debuggingdedicated low-speed serial communication interface circuit is usable inplace of the high-speed serial communication interface circuit forreceiving the system program in the debugging mode.
 4. The microcomputeraccording to claim 3, wherein the debugging dedicated low-speed serialcommunication interface circuit is based on JTAG protocol and includes adata register.
 5. The microcomputer according to claim 3, furthercomprising a trace control circuit, the trace control circuitsuccessively storing, as trace information, an internal state obtainedwhen the central processing unit executes the system program.
 6. Themicrocomputer according to claim 5, wherein the high-speed serialcommunication interface circuit can be utilized for an external outputof the trace information.
 7. A method of developing a system programwhich is to be executed by a target device using a host computer, anemulator, and the target device, comprising: a first process of storinga first system program portion output through high-speed serialcommunication by the host computer in a buffer of a two-plane buffer asa processing to be carried out by the emulator; a second process oftransmitting a second system program portion stored in another buffer ofthe two-plane buffer to the target device through low-speed serialcommunication in parallel with the first process; and a third process ofcarrying out a handshake control of the low-speed serial communicationwith the target device, wherein the second system program portion outputfrom said another buffer is transmitted through the low-speed serialcommunication to the target device via FIFO buffer having a storagecapacity which is equal to or larger than that of said another buffer inthe second process, and a transmission from the FIFO buffer to thetarget device is carried out in response to a transmission permissionsent from the target device, thereby suppressing a transfer from saidanother buffer to the FIFO buffer in response to a full state of theFIFO buffer in the third process.
 8. A microcomputer having a user modeand a debugging mode, comprising: a central processing unit; a universalserial bus interface circuit; a ROM retaining a first debugging controlprogram; a RAM; and an external bus interface circuit, wherein theuniversal serial bus interface circuit has a predetermined endpointbuffer circuit which can be utilized in the debugging mode, thepredetermined endpoint buffer circuit has a pair of buffers which can beoperated in parallel, and one of the buffers can be caused to carry outan input operation and the other buffer can be caused to carry out anoutput operation in parallel therewith, and when the debugging mode isdesignated in a power-on reset, the central processing unit executes thefirst debugging control program to initialize the universal serial businterface circuit to be operable, a second debugging control program isreceived by the universal serial bus interface circuit, the seconddebugging control program thus received is stored in the RAM, and atransition to an execution of the second debugging control programstored in the RAM is made.
 9. The microcomputer according to claim 8,further comprising a buffer RAM and a direct memory access controller,wherein the central processing unit causes the direct memory accesscontroller to transfer the second debugging control program received bythe universal serial bus interface circuit to the buffer RAM in responseto a download request command received by the universal serial businterface circuit in accordance with the second debugging controlprogram.
 10. The microcomputer according to claim 9, wherein the centralprocessing unit causes the direct memory access controller to carry outa control to transfer the second debugging control program transmittedto the buffer RAM through the external bus interface circuit to anoutside in response to a transfer request command received by theuniversal serial bus interface circuit in accordance with the seconddebugging control program.
 11. The microcomputer according to claim 8,wherein the central processing unit makes a transition to the user modein response to a mode control command in an execution state of thesecond debugging control program, and the central processing unitfetches an instruction through the external bus interface circuit in theuser mode.
 12. A microcomputer comprising: a central processing unit; auniversal serial bus interface circuit; a ROM retaining a firstdebugging control program; a buffer RAN; and an external interfacecircuit, wherein the universal serial bus interface circuit has apredetermined endpoint buffer circuit, the predetermined endpoint buffercircuit has a pair of buffers which can be operated in parallel, and oneof the buffers can be caused to carry out an input operation and theother buffer can be caused to carry out an output operation in paralleltherewith, and in a power-on reset, the central processing unit executesthe first debugging control program to initialize the universal serialbus interface circuit to be operable, a second debugging control programis received by the universal serial bus interface circuit, the seconddebugging control program thus received is stored in the buffer RAM, andthe second debugging control program stored in the buffer RAM is outputthrough the external interface circuit.
 13. The microcomputer accordingto claim 12, further comprising a direct memory access controller, thedirect memory access controller transferring the second debuggingcontrol program from the buffer RAM to an outside through the externalinterface circuit in accordance with a transfer control condition set bythe central processing unit.